Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems, among others, often employ electronic components that leverage chip package assemblies for increased functionality and higher component density. Conventional chip packaging schemes often utilize a package substrate, sometimes in conjunction with an interposer, to enable a plurality of integrated circuit (IC) dies to be mounted within a single package. The IC dies may include memory, logic, or other devices.
In some devices, smaller homogenous IC dies are combined within a package to form a larger device. In such case, it is desirable to use the same IC die design for each individual IC the in the package. IC dies having perimeter input/output (IO) circuitry pose challenges for reusing the same IC die to form a larger device in a package. For example, it is problematic to use an IC die having perimeter IO as an “interior” die, i.e., an IC die not on an edge of the package. For interior die, the perimeter IOs are unusable. Further, die-to-die signals have to reach significantly farther, package cavities must grow, interposer costs increase, and static power consumption increases.